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## freenet.support.CPUInformation
Interface CPUInfo

All Known Subinterfaces:
  AMDCPUInfo, IntelCPUInfo, VIACPUInfo

All Known Implementing Classes:
  AMDInfoImpl, IntelInfoImpl, VIAInfoImpl

    public interface CPUInfo

Author:
  Iakin An interface for classes that provide lowlevel information about CPU's free (adj.): unencumbered; not under the control of others Written by Iakin in 2004 and released into the public domain with no warranty of any kind, either expressed or implied. It probably won't make your computer catch on fire, or eat your children, but it might. Use at your own risk.

Method Summary
`String` | `getCPUModelString()`
`String` | `getVendor()`
`boolean` | `hasMMX()`
`boolean` | `hasSSE()`
`boolean` | `hasSSE2()`
`boolean` | `hasSSE3()`
`boolean` | `hasSSE41()`
`boolean` | `hasSSE42()`
`boolean` | `hasSSE4A()`

Method Detail

### getVendor

    String getVendor()

  Returns:
    A string indicating the vendor of the CPU.

### getCPUModelString

    String getCPUModelString()
                             throws UnknownCPUException

  Returns:
    A string detailing what type of CPU that is present in the machine. I.e. 'Pentium IV' etc.
  Throws:
    `UnknownCPUException` - If for any reason the retrieval of the requested information failed. The message encapsulated in the execption indicates the cause of the failure.

### hasMMX

    boolean hasMMX()

  Returns:
    true iff the CPU support the MMX instruction set.

### hasSSE

    boolean hasSSE()

  Returns:
    true iff the CPU support the SSE instruction set.

### hasSSE2

    boolean hasSSE2()

  Returns:
    true iff the CPU support the SSE2 instruction set.

### hasSSE3

    boolean hasSSE3()

  Returns:
    true iff the CPU support the SSE3 instruction set.

### hasSSE41

    boolean hasSSE41()

  Returns:
    true iff the CPU support the SSE4.1 instruction set.

### hasSSE42

    boolean hasSSE42()

  Returns:
    true iff the CPU support the SSE4.2 instruction set.

### hasSSE4A

    boolean hasSSE4A()

  Returns:
    true iff the CPU support the SSE4A instruction set.

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