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sleep.h
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1 /* Copyright (c) 2002, 2004 Theodore A. Roth
2 Copyright (c) 2004, 2007, 2008 Eric B. Weddington
3 Copyright (c) 2005, 2006, 2007 Joerg Wunsch
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 * Redistributions of source code must retain the above copyright
10 notice, this list of conditions and the following disclaimer.
11
12 * Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in
14 the documentation and/or other materials provided with the
15 distribution.
16
17 * Neither the name of the copyright holders nor the names of
18 contributors may be used to endorse or promote products derived
19 from this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE. */
32
33 /* $Id: sleep.h 2238 2011-05-09 16:44:33Z arcanum $ */
34
35 #ifndef _AVR_SLEEP_H_
36 #define _AVR_SLEEP_H_ 1
37
38 #include <avr/io.h>
39 #include <stdint.h>
40
41
42 /** \file */
43
44 /** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
45
46 \code #include <avr/sleep.h>\endcode
47
48 Use of the \c SLEEP instruction can allow an application to reduce its
49 power comsumption considerably. AVR devices can be put into different
50 sleep modes. Refer to the datasheet for the details relating to the device
51 you are using.
52
53 There are several macros provided in this header file to actually
54 put the device into sleep mode. The simplest way is to optionally
55 set the desired sleep mode using \c set_sleep_mode() (it usually
56 defaults to idle mode where the CPU is put on sleep but all
57 peripheral clocks are still running), and then call
58 \c sleep_mode(). This macro automatically sets the sleep enable bit, goes
59 to sleep, and clears the sleep enable bit.
60
61 Example:
62 \code
63 #include <avr/sleep.h>
64
65 ...
66 set_sleep_mode(<mode>);
67 sleep_mode();
68 \endcode
69
70 Note that unless your purpose is to completely lock the CPU (until a
71 hardware reset), interrupts need to be enabled before going to sleep.
72
73 As the \c sleep_mode() macro might cause race conditions in some
74 situations, the individual steps of manipulating the sleep enable
75 (SE) bit, and actually issuing the \c SLEEP instruction, are provided
76 in the macros \c sleep_enable(), \c sleep_disable(), and
77 \c sleep_cpu(). This also allows for test-and-sleep scenarios that
78 take care of not missing the interrupt that will awake the device
79 from sleep.
80
81 Example:
82 \code
83 #include <avr/interrupt.h>
84 #include <avr/sleep.h>
85
86 ...
87 set_sleep_mode(<mode>);
88 cli();
89 if (some_condition)
90 {
91 sleep_enable();
92 sei();
93 sleep_cpu();
94 sleep_disable();
95 }
96 sei();
97 \endcode
98
99 This sequence ensures an atomic test of \c some_condition with
100 interrupts being disabled. If the condition is met, sleep mode
101 will be prepared, and the \c SLEEP instruction will be scheduled
102 immediately after an \c SEI instruction. As the intruction right
103 after the \c SEI is guaranteed to be executed before an interrupt
104 could trigger, it is sure the device will really be put to sleep.
105
106 Some devices have the ability to disable the Brown Out Detector (BOD) before
107 going to sleep. This will also reduce power while sleeping. If the
108 specific AVR device has this ability then an additional macro is defined:
109 \c sleep_bod_disable(). This macro generates inlined assembly code
110 that will correctly implement the timed sequence for disabling the BOD
111 before sleeping. However, there is a limited number of cycles after the
112 BOD has been disabled that the device can be put into sleep mode, otherwise
113 the BOD will not truly be disabled. Recommended practice is to disable
114 the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
115 put the device to sleep (\c sleep_cpu()), like so:
116
117 \code
118 #include <avr/interrupt.h>
119 #include <avr/sleep.h>
120
121 ...
122 set_sleep_mode(<mode>);
123 cli();
124 if (some_condition)
125 {
126 sleep_enable();
127 sleep_bod_disable();
128 sei();
129 sleep_cpu();
130 sleep_disable();
131 }
132 sei();
133 \endcode
134 */
135
136
137 /* Define an internal sleep control register and an internal sleep enable bit mask. */
138 #if defined(SLEEP_CTRL)
139
140 /* XMEGA devices */
141 #define _SLEEP_CONTROL_REG SLEEP_CTRL
142 #define _SLEEP_ENABLE_MASK SLEEP_SEN_bm
143
144 #elif defined(SMCR)
145
146 #define _SLEEP_CONTROL_REG SMCR
147 #define _SLEEP_ENABLE_MASK _BV(SE)
148
149 #elif defined(__AVR_AT94K__)
150
151 #define _SLEEP_CONTROL_REG MCUR
152 #define _SLEEP_ENABLE_MASK _BV(SE)
153
154 #else
155
156 #define _SLEEP_CONTROL_REG MCUCR
157 #define _SLEEP_ENABLE_MASK _BV(SE)
158
159 #endif
160
161
162 /* Define set_sleep_mode() and sleep mode values per device. */
163 #if defined(__AVR_ATmega161__)
164
165 #define SLEEP_MODE_IDLE 0
166 #define SLEEP_MODE_PWR_DOWN 1
167 #define SLEEP_MODE_PWR_SAVE 2
168
169 #define set_sleep_mode(mode) \
170 do { \
171 MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
172 EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
173 } while(0)
174
175
176 #elif defined(__AVR_ATmega162__) \
177 || defined(__AVR_ATmega8515__)
178
179 #define SLEEP_MODE_IDLE 0
180 #define SLEEP_MODE_PWR_DOWN 1
181 #define SLEEP_MODE_PWR_SAVE 2
182 #define SLEEP_MODE_ADC 3
183 #define SLEEP_MODE_STANDBY 4
184 #define SLEEP_MODE_EXT_STANDBY 5
185
186 #define set_sleep_mode(mode) \
187 do { \
188 MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
189 MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
190 EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
191 } while(0)
192
193 #elif defined(__AVR_AT90S2313__) \
194 || defined(__AVR_AT90S2323__) \
195 || defined(__AVR_AT90S2333__) \
196 || defined(__AVR_AT90S2343__) \
197 || defined(__AVR_AT43USB320__) \
198 || defined(__AVR_AT43USB355__) \
199 || defined(__AVR_AT90S4414__) \
200 || defined(__AVR_AT90S4433__) \
201 || defined(__AVR_AT90S8515__) \
202 || defined(__AVR_ATtiny22__)
203
204 #define SLEEP_MODE_IDLE 0
205 #define SLEEP_MODE_PWR_DOWN _BV(SM)
206
207 #define set_sleep_mode(mode) \
208 do { \
209 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~__BV(SM)) | (mode)); \
210 } while(0)
211
212 #elif defined(__AVR_ATtiny167__) \
213 || defined(__AVR_ATtiny87__)
214
215 #define SLEEP_MODE_IDLE 0
216 #define SLEEP_MODE_ADC _BV(SM0)
217 #define SLEEP_MODE_PWR_DOWN _BV(SM1)
218
219 #define set_sleep_mode(mode) \
220 do { \
221 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
222 } while(0)
223
224 #elif defined(__AVR_AT90S4434__) \
225 || defined(__AVR_AT76C711__) \
226 || defined(__AVR_AT90S8535__) \
227 || defined(__AVR_ATmega103__) \
228 || defined(__AVR_ATmega161__) \
229 || defined(__AVR_ATmega163__) \
230 || defined(__AVR_ATmega16HVB__) \
231 || defined(__AVR_ATmega16HVBREVB__) \
232 || defined(__AVR_ATmega32HVB__) \
233 || defined(__AVR_ATmega32HVBREVB__) \
234 || defined(__AVR_ATtiny13__) \
235 || defined(__AVR_ATtiny13A__) \
236 || defined(__AVR_ATtiny15__) \
237 || defined(__AVR_ATtiny24__) \
238 || defined(__AVR_ATtiny24A__) \
239 || defined(__AVR_ATtiny44__) \
240 || defined(__AVR_ATtiny44A__) \
241 || defined(__AVR_ATtiny84__) \
242 || defined(__AVR_ATtiny84A__) \
243 || defined(__AVR_ATtiny25__) \
244 || defined(__AVR_ATtiny45__) \
245 || defined(__AVR_ATtiny48__) \
246 || defined(__AVR_ATtiny85__) \
247 || defined(__AVR_ATtiny88__)
248
249 #define SLEEP_MODE_IDLE 0
250 #define SLEEP_MODE_ADC _BV(SM0)
251 #define SLEEP_MODE_PWR_DOWN _BV(SM1)
252 #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
253
254 #define set_sleep_mode(mode) \
255 do { \
256 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
257 } while(0)
258
259 #elif defined(__AVR_ATtiny2313__) \
260 || defined(__AVR_ATtiny2313A__) \
261 || defined(__AVR_ATtiny4313__)
262
263 #define SLEEP_MODE_IDLE 0
264 #define SLEEP_MODE_PWR_DOWN (_BV(SM0) | _BV(SM1))
265 #define SLEEP_MODE_STANDBY _BV(SM1)
266
267 #define set_sleep_mode(mode) \
268 do { \
269 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
270 } while(0)
271
272 #elif defined(__AVR_AT94K__)
273
274 #define SLEEP_MODE_IDLE 0
275 #define SLEEP_MODE_PWR_DOWN _BV(SM1)
276 #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
277
278 #define set_sleep_mode(mode) \
279 do { \
280 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
281 } while(0)
282
283 #elif defined(__AVR_ATtiny26__) \
284 || defined(__AVR_ATtiny261__) \
285 || defined(__AVR_ATtiny261A__) \
286 || defined(__AVR_ATtiny461__) \
287 || defined(__AVR_ATtiny461A__) \
288 || defined(__AVR_ATtiny861__) \
289 || defined(__AVR_ATtiny861A__) \
290 || defined(__AVR_ATtiny43U__)
291
292 #define SLEEP_MODE_IDLE 0
293 #define SLEEP_MODE_ADC _BV(SM0)
294 #define SLEEP_MODE_PWR_DOWN _BV(SM1)
295 #define SLEEP_MODE_STANDBY (_BV(SM0) | _BV(SM1))
296
297 #define set_sleep_mode(mode) \
298 do { \
299 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
300 } while(0)
301
302 #elif defined(__AVR_AT90PWM216__) \
303 || defined(__AVR_AT90PWM316__) \
304 || defined(__AVR_AT90PWM81__)
305
306 #define SLEEP_MODE_IDLE 0
307 #define SLEEP_MODE_ADC _BV(SM0)
308 #define SLEEP_MODE_PWR_DOWN _BV(SM1)
309 #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
310
311 #define set_sleep_mode(mode) \
312 do { \
313 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
314 } while(0)
315
316 #elif defined(__AVR_AT90CAN128__) \
317 || defined(__AVR_AT90CAN32__) \
318 || defined(__AVR_AT90CAN64__) \
319 || defined(__AVR_AT90PWM1__) \
320 || defined(__AVR_AT90PWM2__) \
321 || defined(__AVR_AT90PWM2B__) \
322 || defined(__AVR_AT90PWM3__) \
323 || defined(__AVR_AT90PWM3B__) \
324 || defined(__AVR_AT90USB162__) \
325 || defined(__AVR_AT90USB82__) \
326 || defined(__AVR_AT90USB1286__) \
327 || defined(__AVR_AT90USB1287__) \
328 || defined(__AVR_AT90USB646__) \
329 || defined(__AVR_AT90USB647__) \
330 || defined(__AVR_ATmega128__) \
331 || defined(__AVR_ATmega1280__) \
332 || defined(__AVR_ATmega1281__) \
333 || defined(__AVR_ATmega1284P__) \
334 || defined(__AVR_ATmega128RFA1__) \
335 || defined(__AVR_ATmega16__) \
336 || defined(__AVR_ATmega16A__) \
337 || defined(__AVR_ATmega162__) \
338 || defined(__AVR_ATmega164A__) \
339 || defined(__AVR_ATmega164P__) \
340 || defined(__AVR_ATmega165__) \
341 || defined(__AVR_ATmega165A__) \
342 || defined(__AVR_ATmega165P__) \
343 || defined(__AVR_ATmega168__) \
344 || defined(__AVR_ATmega168A__) \
345 || defined(__AVR_ATmega168P__) \
346 || defined(__AVR_ATmega169__) \
347 || defined(__AVR_ATmega169A__) \
348 || defined(__AVR_ATmega169P__) \
349 || defined(__AVR_ATmega169PA__) \
350 || defined(__AVR_ATmega16HVA__) \
351 || defined(__AVR_ATmega16HVA2__) \
352 || defined(__AVR_ATmega16M1__) \
353 || defined(__AVR_ATmega16U2__) \
354 || defined(__AVR_ATmega16U4__) \
355 || defined(__AVR_ATmega2560__) \
356 || defined(__AVR_ATmega2561__) \
357 || defined(__AVR_ATmega32__) \
358 || defined(__AVR_ATmega323__) \
359 || defined(__AVR_ATmega324A__) \
360 || defined(__AVR_ATmega324P__) \
361 || defined(__AVR_ATmega324PA__) \
362 || defined(__AVR_ATmega325__) \
363 || defined(__AVR_ATmega325A__) \
364 || defined(__AVR_ATmega3250__) \
365 || defined(__AVR_ATmega3250A__) \
366 || defined(__AVR_ATmega328__) \
367 || defined(__AVR_ATmega328P__) \
368 || defined(__AVR_ATmega329__) \
369 || defined(__AVR_ATmega329A__) \
370 || defined(__AVR_ATmega329P__) \
371 || defined(__AVR_ATmega329PA__) \
372 || defined(__AVR_ATmega3290__) \
373 || defined(__AVR_ATmega3290A__) \
374 || defined(__AVR_ATmega3290P__) \
375 || defined(__AVR_ATmega32C1__) \
376 || defined(__AVR_ATmega32M1__) \
377 || defined(__AVR_ATmega32U2__) \
378 || defined(__AVR_ATmega32U4__) \
379 || defined(__AVR_ATmega32U6__) \
380 || defined(__AVR_ATmega406__) \
381 || defined(__AVR_ATmega48__) \
382 || defined(__AVR_ATmega48A__) \
383 || defined(__AVR_ATmega48P__) \
384 || defined(__AVR_ATmega64__) \
385 || defined(__AVR_ATmega640__) \
386 || defined(__AVR_ATmega644__) \
387 || defined(__AVR_ATmega644A__) \
388 || defined(__AVR_ATmega644P__) \
389 || defined(__AVR_ATmega644PA__) \
390 || defined(__AVR_ATmega645__) \
391 || defined(__AVR_ATmega645A__) \
392 || defined(__AVR_ATmega645P__) \
393 || defined(__AVR_ATmega6450__) \
394 || defined(__AVR_ATmega6450A__) \
395 || defined(__AVR_ATmega6450P__) \
396 || defined(__AVR_ATmega649__) \
397 || defined(__AVR_ATmega649A__) \
398 || defined(__AVR_ATmega6490__) \
399 || defined(__AVR_ATmega6490A__) \
400 || defined(__AVR_ATmega6490P__) \
401 || defined(__AVR_ATmega649P__) \
402 || defined(__AVR_ATmega64C1__) \
403 || defined(__AVR_ATmega64HVE__) \
404 || defined(__AVR_ATmega64M1__) \
405 || defined(__AVR_ATmega8__) \
406 || defined(__AVR_ATmega8515__) \
407 || defined(__AVR_ATmega8535__) \
408 || defined(__AVR_ATmega88__) \
409 || defined(__AVR_ATmega88A__) \
410 || defined(__AVR_ATmega88P__) \
411 || defined(__AVR_ATmega88PA__) \
412 || defined(__AVR_ATmega8HVA__) \
413 || defined(__AVR_ATmega8U2__)
414
415
416 #define SLEEP_MODE_IDLE (0)
417 #define SLEEP_MODE_ADC _BV(SM0)
418 #define SLEEP_MODE_PWR_DOWN _BV(SM1)
419 #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
420 #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
421 #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
422
423
424 #define set_sleep_mode(mode) \
425 do { \
426 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
427 } while(0)
428
429 #elif defined(__AVR_ATxmega16A4__) \
430 || defined(__AVR_ATxmega16D4__) \
431 || defined(__AVR_ATxmega32A4__) \
432 || defined(__AVR_ATxmega32D4__) \
433 || defined(__AVR_ATxmega64A1__) \
434 || defined(__AVR_ATxmega64A1U__) \
435 || defined(__AVR_ATxmega64A3__) \
436 || defined(__AVR_ATxmega64D3__) \
437 || defined(__AVR_ATxmega128A1__) \
438 || defined(__AVR_ATxmega128A1U__) \
439 || defined(__AVR_ATxmega128A3__) \
440 || defined(__AVR_ATxmega128D3__) \
441 || defined(__AVR_ATxmega192A3__) \
442 || defined(__AVR_ATxmega192D3__) \
443 || defined(__AVR_ATxmega256A3__) \
444 || defined(__AVR_ATxmega256D3__) \
445 || defined(__AVR_ATxmega256A3B__)
446
447 #define SLEEP_MODE_IDLE (0)
448 #define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
449 #define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
450 #define SLEEP_MODE_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
451 #define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
452
453 #define set_sleep_mode(mode) \
454 do { \
455 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
456 } while(0)
457
458 #elif defined(__AVR_AT90SCR100__)
459
460 #define SLEEP_MODE_IDLE (0)
461 #define SLEEP_MODE_PWR_DOWN _BV(SM1)
462 #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
463 #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
464 #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
465
466 #define set_sleep_mode(mode) \
467 do { \
468 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
469 } while(0)
470
471 #elif defined(__AVR_ATA6289__)
472
473 #define SLEEP_MODE_IDLE (0)
474 #define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0))
475 #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
476
477 #define set_sleep_mode(mode) \
478 do { \
479 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
480 } while(0)
481
482 #elif defined(__AVR_ATtiny4__) \
483 || defined(__AVR_ATtiny5__) \
484 || defined(__AVR_ATtiny9__) \
485 || defined(__AVR_ATtiny10__) \
486 || defined(__AVR_ATtiny20__) \
487 || defined(__AVR_ATtiny40__)
488
489 #define SLEEP_MODE_IDLE 0
490 #define SLEEP_MODE_ADC _BV(SM0)
491 #define SLEEP_MODE_PWR_DOWN _BV(SM1)
492 #define SLEEP_MODE_STANDBY _BV(SM2)
493
494 #define set_sleep_mode(mode) \
495 do { \
496 _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
497 } while(0)
498
499 #else
500
501 #error "No SLEEP mode defined for this device."
502
503 #endif
504
505
506
507 /** \ingroup avr_sleep
508
509 Put the device in sleep mode. How the device is brought out of sleep mode
510 depends on the specific mode selected with the set_sleep_mode() function.
511 See the data sheet for your device for more details. */
512
513
514 #if defined(__DOXYGEN__)
515
516 /** \ingroup avr_sleep
517
518 Set the SE (sleep enable) bit.
519 */
520 extern void sleep_enable (void);
521
522 #else
523
524 #define sleep_enable() \
525 do { \
526 _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \
527 } while(0)
528
529 #endif
530
531
532 #if defined(__DOXYGEN__)
533
534 /** \ingroup avr_sleep
535
536 Clear the SE (sleep enable) bit.
537 */
538 extern void sleep_disable (void);
539
540 #else
541
542 #define sleep_disable() \
543 do { \
544 _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \
545 } while(0)
546
547 #endif
548
549
550 /** \ingroup avr_sleep
551
552 Put the device into sleep mode. The SE bit must be set
553 beforehand, and it is recommended to clear it afterwards.
554 */
555 #if defined(__DOXYGEN__)
556
557 extern void sleep_cpu (void);
558
559 #else
560
561 #define sleep_cpu() \
562 do { \
563 __asm__ __volatile__ ( "sleep" "\n\t" :: ); \
564 } while(0)
565
566 #endif
567
568
569 #if defined(__DOXYGEN__)
570
571 extern void sleep_mode (void);
572
573 #else
574
575 #define sleep_mode() \
576 do { \
577 sleep_enable(); \
578 sleep_cpu(); \
579 sleep_disable(); \
580 } while (0)
581
582 #endif
583
584
585 #if defined(__DOXYGEN__)
586
587 extern void sleep_bod_disable (void);
588
589 #else
590
591 #if defined(BODS) && defined(BODSE)
592
593 #define sleep_bod_disable() \
594 do { \
595 uint8_t tempreg; \
596 __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
597 "ori %[tempreg], %[bods_bodse]" "\n\t" \
598 "out %[mcucr], %[tempreg]" "\n\t" \
599 "andi %[tempreg], %[not_bodse]" "\n\t" \
600 "out %[mcucr], %[tempreg]" \
601 : [tempreg] "=&d" (tempreg) \
602 : [mcucr] "I" _SFR_IO_ADDR(MCUCR), \
603 [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
604 [not_bodse] "i" (~_BV(BODSE))); \
605 } while (0)
606
607 #endif
608
609 #endif
610
611
612 /*@}*/
613
614 #endif /* _AVR_SLEEP_H_ */

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