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Topic Title: EDA-Tools
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Created On: 17-Apr-2006 14:49
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 17-Apr-2006 14:49
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Brandi Carroll

Posts: 82
Joined: 22-Jul-2004

EDA-Tools

Chemnitz University of Technology
[url]http://www.tu-chemnitz.de/etit/sse/[/url]

Instructor: Prof. Ulrich Heinkel, Uwe Pross
Email: [email]ulrich.heinkel@etit.tu-chemnitz.de[/email]
[email]uwe.pross@e-technik.tu-chemnitz.de[/email]

Prerequisites
? Course Circuit Design (ASICs Basics)
? Course System Design (VHDL Basics)

Course description
Students will learn different flows and tools for system and circuit design starting from specification level down to gate level. Objective is to introduce common flows and tools and discuss their advantages, disadvantages and their limits. After the course students are able to make decision which tools can be used in order to solve a given task.
The following topics are covered:
➢ Overview (2 lectures)
? Why EDA?, ICs, design-gap, design productivity, design steps, IC-manufacturing
? Design-flow
? V-Model, abstraction layers, tools
➢ System specification (2 lectures, 1 lab session)
? Product concept catalog, customer requirement specification, design
safeness
? Refinement, partitioning
➢ Petri-Nets (2 lectures, 2 lab sessions)
? Basics of Place-Transition Nets
? Colored PTN
? Modeling using PTNs
➢ Statemate
? State coverage, formal verification
? Applications
➢ SystemC (1 lecture, 2 lab sessions)
? Overview, comparison to VHDL, applications
➢ Matlab/Simulink (1 lecture)
? Overview, applications
➢ UML (2 lecture, 2 lab sessions)
? Basic ideas
? Diagram types
? Modeling example
➢ VHDL (2 lecture, 2 lab sessions)
? Synthesizable subset
? Simulation, Libraries, Linting
? Reuse
➢ Formal Verification (1 lecture, 1 lab sessions)
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